DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 246

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

7–2
Figure 7–1. External Memory Interface Datapath Overview for Stratix V Devices
Notes to
(1) You can bypass each register block.
(2) The blocks for each memory interface may differ slightly. The shaded blocks are part of the Stratix V IOE.
(3) These signals may be bidirectional or unidirectional, depending on the memory standard. When bidirectional, the signal is active during both read
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
and write operations.
Clock Management
Figure
and Reset
7–1:
f
Figure 7–1
Stratix V IOE features.
Memory interfaces use Stratix V device features such as delay-locked loops (DLLs),
dynamic OCT control, read- and write-leveling circuitry, and I/O features such as
programmable I/O delay chains, read FIFO blocks, slew rate adjustment, and
programmable drive strength.
For more information about I/O features, refer to the
chapter.
The UniPHY megafunction instantiates a phase-locked loop (PLL) to generate related
clocks for the memory interface.
Postamble Clock
DQ Write Clock
Half-Rate Clock
Alignment Clock
DQS Write Clock
shows an overview of the memory interface datapath that uses all the
4n
4
Half Data
Registers
Half Data
Registers
4n
Output
DLL
Output
Rate
Rate
Read FIFO
2n
2
Postamble Enable
DQS Logic
Alignment
Alignment
Registers
Registers
Chapter 7: External Memory Interfaces in Stratix V Devices
Block
2n
2n
2
(Note
DQS Enable
DDR Output
DDR Output
I/O Features in Stratix V Devices
and Output
DDR Input
and Output
Registers
Registers
Registers
Stratix V FPGA
Enable
Control
Enable
Enable
Circuit
Circuit
DQS
1),
(2)
May 2011 Altera Corporation
n
n
DQS (Read) (3)
DQ (Read) (3)
DQ (Write) (3)
DQS (Write) (3)
Memory