DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 430

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DK-DEV-5SGXEA7/ES

Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Datasheets

Specifications of DK-DEV-5SGXEA7/ES

Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
2–14
Stratix V Device Handbook Volume 3: Transceivers
Figure 2–11. Six Transmit-Only Channels Configured in Bonded Configuration
Note to
(1) Serial clock from the ×1 clock lines.
Figure
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Parallel Clock
Serial Clock
Parallel and Serial Clocks
CMU PLL
CMU PLL
CMU PLL
CMU PLL
CMU PLL
CMU PLL
2–11:
Low-Speed Parallel Clock
High-Speed Serial Clock
Low-Speed Parallel Clock
High-Speed Serial Clock
(1)
(1)
(1)
(1)
(1)
(1)
Local Clock Divider
Central Clock Divider
Local Clock Divider
Local Clock Divider
Central Clock Divider
Local Clock Divider
Transmitter PCS
Transmitter PCS
Transmitter PCS
Transmitter PCS
Transmitter PCS
Transmitter PCS
Clock Divider
Clock Divider
Clock Divider
Clock Divider
Clock Divider
Clock Divider
Chapter 2: Transceiver Clocking in Stratix V Devices
Transmitter PMA
Transmitter PMA
Transmitter PMA
Transmitter PMA
Transmitter PMA
Transmitter PMA
Serializer
Serializer
Serializer
Serializer
Serializer
Serializer
May 2011 Altera Corporation
×6 Clock Line
Internal Clocking
×6 Clock Line

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