DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 488

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–32
Stratix V Device Handbook Volume 3: Transceivers
Supported Features
1
Table 4–6
functions are defined in the IEEE 802.3-2008 GIGE protocol definition, Section 3
Clause 36.
Table 4–6. Supported Features in a GIGE Configuration
8B/10B Encoding/Decoding
In GIGE mode, the 8B/10B encoder clocks in 8-bit data and 1-bit control identifiers
from the transmitter phase compensation FIFO and generates 10-bit encoded data.
8B/10B encoding limits the maximum number of consecutive 1s and 0s in the serial
data stream to five, thereby ensuring DC balance as well as enough transitions for the
receiver CDR to maintain a lock to the incoming data. The 10-bit encoded data is then
fed to the serializer for transmission.
The 8B/10B decoder parses the serial stream of code groups from the rate match FIFO
block and recovers the 8-bit data and control characters. The GIGE Custom PHY IP
provides a running disparity error, run length violation error, and invalid 8B/10B
code group error status ports.
Idle Ordered-Set Generation/Substitution
The IEEE 802.3 specification requires the GIGE PHY to transmit idle ordered sets (/I/)
continuously and repetitively whenever the GMII is idle. This ensures that the
receiver maintains bit and word synchronization whenever there is no active data to
be transmitted. Idle ordered-set substitution must be implemented in a PLD logic
array.
In GIGE functional mode, any /Dx.y/ following a /K28.5/ comma is replaced by the
transmitter with either a /D5.6/ (/I1/ ordered set) or a /D16.2/ (/I2/ ordered set),
depending on the current running disparity. The exception is when the data following
the /K28.5/ is /D21.5/ (/C1/ ordered set) or /D2.2/ (/C2/) ordered set. If the
running disparity before the /K28.5/ is positive, an /I1/ ordered set is generated. If
the running disparity is negative, a /I2/ ordered set is generated. The disparity at the
end of a /I1/ is the opposite of that at the beginning of the /I1/. The disparity at the
end of a /I2/ is the same as the beginning running disparity (right before the idle
code). This ensures a negative running disparity at the end of an idle ordered set. A
/Kx.y/ following a /K28.5/ is not replaced.
Note that /D14.3/, /D24.0/, and /D15.8/ are replaced by /D5.6/ or /D16.2/ (for
/I1/, /I2/ ordered sets). /D21.5/ (part of the /C1/ order set) is not replaced.
8B/10B Encoding/Decoding
Synchronization
Clock Compensation using Rate Matching
lists the GIGE-PCS functions that are supported by Stratix V devices. These
Feature
Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
May 2011 Altera Corporation
Supported
v
v
v
GIGE