DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 342

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

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Stratix V Device Handbook Volume 2: Device Interfaces and Integration
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The Stratix V device error detection CRC feature does not check memory blocks and
I/O buffers. Thus, the CRC_ERROR signal may stay solid high or low, depending on the
error status of the previously checked CRAM frame. The I/O buffers are not verified
during error detection because these bits use flipflops as storage elements that are
more resistant to soft errors when compared with CRAM cells. MLAB and M20K
memory blocks support parity bits that are used to check the contents of memory
blocks for any error.
For more information about error detection in Stratix V memory blocks, refer to the
TriMatrix Embedded Memory Blocks in Stratix V Devices
In Stratix V, in addition to the error detection capability, the error detection circuitry
also supports error correction or internal scrubbing, which is an ability to internally
correct soft errors that have been detected. This is done on a per-frame basis. If
internal scrubbing is enabled, the device corrects single-bit error or double-adjacent
error in the CRAM bits while the device is still running.
To provide testing capability of the error detection block, a JTAG instruction,
EDERROR_INJECT, is provided. This instruction is able to change the content of the
47-bit JTAG fault injection register used for error injection in Stratix V devices, thereby
enabling testing of the error detection block.
You can only execute the EDERROR_INJECT JTAG instruction when the device is in user
mode.
Table 10–3
Table 10–3. EDERROR_INJECT JTAG Instruction
You can create a Jam™ file (.jam) to automate the testing and verification process.
This allows you to verify the CRC functionality in-system and on-the-fly, without
having to reconfigure the device. You can then switch to the CRC circuit to check for
real errors induced by a SEU.
You can introduce a single error or double errors adjacent to each other to the
configuration memory. This provides an extra way to facilitate design verification and
system fault tolerance characterization. Use the JTAG fault injection register with the
EDERROR_INJECT JTAG instruction to flip the readback bits. The Stratix V device is then
forced into error test mode. Altera recommends reconfiguring the device after the test
completes.
You can only introduce error injection in the first data frame, but you can monitor the
error information at any time. For more information about the JTAG fault injection
register and fault injection register, refer to
EDERROR_INJECT
JTAG Instruction
lists the EDERROR_INJECT JTAG instruction.
Instruction Code
00 0001 0101
“Error Detection Registers” on page
This instruction controls the 47-bit JTAG fault
injection register used for error injection.
Chapter 10: SEU Mitigation in Stratix V Devices
chapter.
User Mode Error Detection and Correction
Description
May 2011 Altera Corporation
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