DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 152

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Table 4–3. Clock Input Pin Connectivity to the RCLK Networks (Part 3 of 3)—Preliminary
RCLK
[40,41,42,43,44,
45,67,88]
RCLK [71,75,78,82] — — — — — — — —
RCLK [72,76,79,83] — — — — — — — —
RCLK [73,77,80,84] — — — — — — — —
RCLK [74,81]
Notes to
(1) This is applicable to all Stratix V devices except 5SGSD6 and 5SGSD8 devices.
(2) This is only applicable to 5SGSD6, 5SGSD8 devices.
Clock Resources
Table
4–3:
— — — — — — — —
— — — — — — — —
0
1
2
3
4
5
6
7
—
—
—
—
—
8
—
—
—
—
—
9
10
—
—
—
—
—
11
—
—
—
—
—
12
—
—
—
—
—
CLK (p/n pins)
13
—
—
—
—
—
14
—
—
—
—
—
15
—
—
—
—
—
16 17 18 19 20 21 22 23
— — — — — — — v
— — — — — — — —
— — — — — — — —
— — — — — — — —
— — — — — — — —
v
24
—
(2)
—
—
—
25
—
—
v
—
—
(2)
26
—
—
—
v
—
(2)
v
27
—
—
—
—
(2)