DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 507

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 5: Transceiver Custom Configurations in Stratix V Devices
10G Low Latency Configuration
Figure 5–4. 10G PCS Low Latency Datapath with Gear Box Not Enabled
May 2011 Altera Corporation
tx_clkout
rx_clkout
Fabric
FPGA
f
CMU PLL
(From the ×1 Clock Lines)
TX Bit Slip Feature
The bit slip feature supported in custom configurations enables you to slip the
transmit side bits before they are sent to the gear box. The number of bits slipped is
equal to the FPGA fabric-to-transceiver interface width of 1. For example, if the FPGA
fabric-to-transceiver interface width is 64 bits, a maximum of 63 bits can be slipped.
That is, bits[63] from the first word and bits[62:0] are concatenated to form a 64 bit
word (bit[62:0] from the second word, bit[63] from the first word LSB). The 7-bit
input control signal is available to the FPGA fabric. For a 63-bit shift mentioned
above, set the value of the input control to 7'b0011111.
Clocking
This section describes the transceiver datapath clocking.
clocking scheme when the gear box is not enabled. There is no frequency difference
between the read and write side of the TX and RX FIFO clocks because the gear box is
not enabled. The Quartus II software automatically connects the clocks to the read
and write side of the TX FIFO and RX FIFO. In this configuration, the data from the
TX FIFO is directly fed to the serializer.
For more information about the channel PLL, refer to “Channel PLL Architecture” in
the
Serial Clock
Transceiver Architecture of Stratix V Devices
Central/ Local Clock Divider
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Clock Divider
Parallel and Serial Clocks
(Only from the Central Clock Divider)
chapter.
Stratix V Device Handbook Volume 3: Transceivers
Transmitter 10G PCS
Receiver 10G PCS
Figure 5–4
shows the
Transmitter PMA
Parallel Clock
Serial Clock
Parallel Clock andSerial Clock
Receiver PMA
Input Reference
Clock
5–5