DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 155

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Clock Networks and PLLs in Stratix V Devices
Clock Networks in Stratix V Devices
May 2011 Altera Corporation
You can select the HSSI output or internal logic to drive the HSSI horizontal PCLK
control block. Alternatively, you can also use the DPA clock output or internal logic to
drive the DPA horizontal PCLK. You can only use the DPA output to generate the
vertical PCLK to the core.
Figure 4–11. Horizontal PCLK Control Block
You can power down the Stratix V GCLK and RCLK clock networks using both static
and dynamic approaches. When a clock network is powered down, all the logic fed by
the clock network is in off-state, thereby reducing the overall power consumption of
the device. The unused GCLK, RCLK, and PCLK networks are automatically powered
down through configuration bit settings in the configuration file (.sof or .pof)
generated by the Quartus II software. The dynamic clock enable or disable feature
allows the internal logic to control power-up or power-down synchronously on the
GCLK and RCLK networks, including dual-regional clock regions.
Figure 4–10
on the clock network.
show that this function is independent of the PLL and is applied directly
DPA clock output
HSSI output or
Horizontal PCLK
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Internal logic
Static Clock Select
Figure 4–9
and
4–15