DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 315

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
JTAG Configuration
Figure 9–21. JTAG Configuration of a Single Device Using a Download Cable
Notes to
(1) Connect the pull-up resistor V
(2) If you only use JTAG configuration, connect nCONFIG to V
(3) The resistor value can vary from 1 k
(4) You must connect nCE to GND or drive it low for successful JTAG configuration.
May 2011 Altera Corporation
on your board. If you are using JTAG in conjunction with another configuration scheme, connect MSEL[4..0], nCONFIG and DCLK based on
the selected configuration scheme.
Figure
9–21:
f
V
CCPGM
Figure 9–21
Alternatively, you can use a microprocessor to program the device through the JTAG
interface. You can use JRunner as your software driver.
For more information about JRunner, refer to
Embedded Solution for PLD JTAG
CCPD
V
CCPGM
. For more information, refer to V

GND
to 10 k
shows the JTAG configuration of a single Stratix V device.
(2)
(2)
(2)
N.C.

. Perform signal integrity analysis to select the resistor value for your setup.
nCE
nCEO
nSTATUS
CONF_DONE
nCONFIG
MSEL[4..0]
DCLK
Stratix V Device
CCPGM
and MSEL[4..0] to GND. Pull DCLK either high or low, whichever is convenient
TRST
TDO
TMS
TCK
CCPD
TDI
Configuration.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
requirement in
V
CCPD
V
CCPD
(1)
V
(3)
(1)
CCPD
(3)
(1)
AN 414: The JRunner Software Driver: An
“V
CCPD
GND
Pin 1
Pin” on page
(JTAG Mode) (Top View)
10-Pin Male Header
Download Cable
GND
9–3.
V
CCPD
GND
(1)
9–35