DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 247

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 7: External Memory Interfaces in Stratix V Devices
Memory Interface Pin Support
Memory Interface Pin Support
Figure 7–2. Memory Clock Generation
Notes to
(1) To minimize jitter, a dedicated clock network is used for memory output clock generation.
May 2011 Altera Corporation
Figure
7–2:
f
f
System Clock (1)
For more information about the Stratix V PLL, refer to the
Stratix V Devices
refer to
Interface Handbook.
A typical memory interface requires data (D, Q, or DQ), data strobe (DQS/CQ/QK
and DQSn/CQn, QK#), address, command, and clock pins. Some memory interfaces
use data mask (DM, BWSn, or NWSn) pins to enable write masking and QVLD pins to
indicate that the read data is ready to be captured. This section describes how
Stratix V devices support all these different pins.
DDR3 and DDR2 SDRAM, and RLDRAM II devices use the CK and CK# signals to
capture the address and command signals. Generate these signals to mimic the
write-data strobe with Stratix V DDR I/O (DDRIO) registers to ensure that the timing
relationships between the CK/CK# and DQS signals (t
and DDR2 SDRAM devices or t
QDR II SRAM devices use the same clock (K/K#) to capture write data, address, and
command signals.
Memory clock pins in Stratix V devices are generated with a DDRIO register going to
differential output pins (refer to
DIFFIO_TX, or DIFFIO_RX prefixes.
For more information about which pins to use for memory clock pins and pin location
requirements, refer to the
Memory Interface Handbook.
Stratix V devices offer differential input buffers for differential read-data strobe and
clock operations. In addition, Stratix V devices also provide an independent DQS
logic block for each CQn pin for complementary read-data strobe and clock
operations. In the Stratix V pin tables, the differential data strobe/clock pin pairs are
denoted as DQS and DQSn pins, while the complementary echo clock signals are
denoted as CQ and CQn pins. DQSn and CQn pins are marked separately in the pin
tables. Each CQn pin connects to a DQS logic block and the phase-shifted CQn signals
go to the negative-half cycle input registers in the DQ IOE registers.
V CC
Volume 3: Implementing Altera Memory Interface IP
(Note 1)
chapter. For more information about the UniPHY megafunction,
Section I: Device and Pin Planning
CKDK
Figure
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
D
D
in RLDRAM II devices) are met. QDR II+ and
7–2), marked in the pin table with DIFFOUT,
Q
Q
0
1
DQSS
of the External Memory
Clock Networks and PLLs in
in volume 2 of the External
, t
DSS
, and t
mem_clk
mem_clk_n
DSH
in DDR3
7–3