DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 204

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

5–28
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Differential I/O Standards Termination
Stratix V devices support differential SSTL-18 and SSTL-2, differential HSTL-18,
HSTL-15, HSTL-12, LVDS, LVPECL, RSDS, and mini-LVDS I/O standards.
Figure 5–15
terminations on these devices.
The supported I/O standards such as differential SSTL-12, differential SSTL-15,
differential SSTL-125, and differential SSTL-135 typically do not require external
board termination. Altera recommends using these I/O standards with dynamic OCT
schemes to save board space and costs by reducing the number of external
termination resistors used.
through
Figure 5–21
show the details of various differential I/O
Chapter 5: I/O Features in Stratix V Devices
Termination Schemes for I/O Standards
May 2011 Altera Corporation