DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 168

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–28
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Direct Compensation Mode
In direct compensation mode, the PLL does not compensate for any clock networks.
This mode provides better jitter performance because the clock feedback into the PFD
passes through less circuitry. Both the PLL internal- and external-clock outputs are
phase-shifted with respect to the PLL clock input.
waveform of the PLL clocks’ phase relationship in direct compensation mode.
Figure 4–23. Phase Relationship Between the PLL Clocks in Direct Compensation Mode
Note to
(1) The PLL clock outputs lag the PLL input clocks depending on routine delays.
Normal Mode
An internal clock in normal mode is phase-aligned to the input clock pin. The external
clock-output pin has a phase delay relative to the clock input pin if connected in this
mode. The Quartus II software timing analyzer reports any phase difference between
the two. In normal mode, the delay introduced by the GCLK or RCLK network is fully
compensated.
relationship in normal mode.
Figure 4–24. Phase Relationship Between the PLL Clocks in Normal Mode
Note to
(1) The external clock output can lead or lag the PLL internal clock signals.
Figure
Figure
Dedicated PLL Clock Outputs (1)
External PLL Clock Outputs (1)
4–23:
4–24:
Figure 4–24
Register Clock Port (1)
Register Clock Port
PLL Clock at the
PLL Clock at the
PLL Reference
PLL Reference
Clock at the
Clock at the
Input Pin
Input Pin
shows an example waveform of the PLL clocks’ phase
Phase Aligned
Phase Aligned
Chapter 4: Clock Networks and PLLs in Stratix V Devices
Figure 4–23
shows an example
May 2011 Altera Corporation
Stratix V PLLs