DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 451

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 3: Transceiver Reset Control in Stratix V Devices
Transceiver Reset Sequence
Transceiver Reset Sequence
May 2011 Altera Corporation
Reset Sequence for CDR in Automatic Lock Mode
1
The recommended transceiver reset sequence is divided into two categories:
■
■
Figure 3–2
automatic lock mode. The reset sequence is implemented automatically by the
embedded reset controller. After device power-up, the reset controller initiates the
reset sequence when it receives a positive edge on the phy_mgmt_clk_reset input
signal. The reset controller then indicates that the transmitter and receiver channels
are ready for data transmission and reception by asserting the tx_ready and rx_ready
signals, respectively.
After the initial reset sequence, the reset controller continuously monitors all the
status signals and asserts the appropriate reset signals is case of loss of link or loss of
reference clock.
The reset sequence for PIPE follows the same reset sequence as the CDR in automatic
lock mode.
Reset sequence for CDR in automatic lock mode
Reset sequence for CDR in manual lock mode
shows the timing diagram of the transceiver reset sequence for CDR in
Stratix V Device Handbook Volume 3: Transceivers
3–3