DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 473

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
PCI Express (PCIe)—Gen1 and Gen2
Figure 4–12. Stratix V Transmitter Channel Datapath in a PCIe Configurations
Table 4–4. Supported Features in PCIe Configurations
May 2011 Altera Corporation
×1, ×4, ×8 link configurations
PCIe-compliant synchronization state machine
±300 PPM (total 600 PPM) clock rate compensation
8-bit FPGA fabric-transceiver interface
16-bit FPGA fabric-transceiver interface
Transmitter buffer electrical idle
Receiver Detection
8B/10B encoder disparity control when transmitting compliance pattern
Power state management
Receiver status encoding
Dynamic switching between 2.5 Gbps and 5 Gbps signaling rate
Dynamically selectable transmitter margining for differential output voltage control
Dynamically selectable transmitter buffer de-emphasis of -3.5 dB and -6 dB
Fabric
FPGA
Supported Features
f
Transceiver Channel Datapath
Figure 4–12
configuration.
For more information about the blocks in the transmitter datapath, refer to the
Transceiver Architecture in Stratix V Devices
Table 4–4
5 Gbps data rate configurations.
lists the features supported in a PCIe configuration for the 2.5 Gbps and
shows the Stratix V transmitter and receiver channel datapath in a PCIe
Feature
Transmitter PCS
Receiver PCS
chapter.
Stratix V Device Handbook Volume 3: Transceivers
(12.5 Gbps)
Gen1
v
v
v
v
v
v
v
v
v
v
—
—
—
Transmitter PMA
(5 Gbps)
Receiver PMA
Gen2
v
v
v
v
v
v
v
v
v
v
v
v
—
4–17