DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 463

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
10GBASE-R
Figure 4–5. 10GBASE-R Single-Lane Configuration
May 2011 Altera Corporation
Fabric
FPGA
xgmii_tx_clk (156.25MHz)
xgmii_rx_clk (156.25MHz)
Transceiver Clocking and Channel Placement Guidelines
64
64
Divider
Divider
CMU PLL
(From the ×1 Clock Lines)
This section describes the transceiver clocking and channel placement guidelines for
the 10GBASE-R protocol supported in Stratix V devices.
Transceiver Clocking
Figure 4–5
One of the two channel phase-locked loops (PLLs) or one of the two auxiliary transmit
(ATX) PLLs in a transceiver bank generates the transmitter serial and parallel clocks
for the 10GBASE-R channel(s).
FPGA fabric-transceiver interface width, and the interface frequency supported in a
10GBASE-R configuration.
Table 4–2. Input Reference Clock Frequency and Interface Speed Specifications for 10GBASE-R
Configurations
Serial Clock
644.53125, 322.265625
Input Reference Clock
Frequency (MHz)
shows transceiver clocking in a 10GBASE-R configuration.
Central/ Local Clock Divider
Monitor
BER
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Paralell Clock (Recovered) (257.8125 MHz)
Paralell Clock (257.8125 MHz)
FPGA Fabric-Transceiver
64-bit data, 8-bit control
Table 4–2
Clock Divider
Interface Width
lists the input reference clock frequency,
Stratix V Device Handbook Volume 3: Transceivers
Transmitter 10G PCS
Receiver 10G PCS
FPGA Fabric-Transceiver
Interface Width (MHz)
40
40
156.25
Transmitter PMA
Receiver PMA
Parallel Clock
Serial Clock
Parallel and Serial Clocks
4–7