DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 60

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

2–32
Table 2–36. Glossary (Part 3 of 4)
Stratix V Device Handbook Volume 1: Overview and Datasheet
Letter
S
U
T
SW (sampling
window)
Single-ended
voltage
referenced I/O
standard
t
TCCS (channel-
to-channel-skew)
t
t
t
t
t
t
C
DUTY
FALL
INCCJ
OUTPJ_IO
OUTPJ_DC
RISE
Subject
—
Timing Diagram—the period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position within the sampling
window, as shown:
The JEDEC standard for SSTl and HSTL I/O defines both the AC and DC input signal values.
The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input has crossed the AC value, the
receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the AC threshold.
This approach is intended to provide predictable receiver timing in the presence of input
waveform ringing, as shown:
Single-Ended Voltage Referenced I/O Standard
High-speed receiver and transmitter input and output clock period.
The timing difference between the fastest and slowest output edges, including t
and clock skew, across channels driven by the same PLL. The clock is included in the TCCS
measurement (refer to the Timing Diagram figure under SW in this table).
High-speed I/O block—Duty cycle on the high-speed transmitter output clock.
Timing Unit Interval (TUI)
The timing budget allowed for skew, propagation delays, and the data sampling window.
(TUI = 1/(receiver input clock frequency multiplication factor) = t
Signal high-to-low transition time (80-20%)
Cycle-to-cycle jitter tolerance on the PLL clock input.
Period jitter on the general purpose I/O driven by a PLL.
Period jitter on the dedicated clock output driven by a PLL.
Signal low-to-high transition time (20-80%)
0.5 x TCCS
V
V
OH
OL
RSKM
Sampling Window
Bit Time
(SW)
Chapter 2: DC and Switching Characteristics for Stratix V Devices
V
REF
Definitions
RSKM
—
0.5 x TCCS
V
V
IH(DC)
IL(DC)
C
V
V
/w)
IH ( AC )
IL(AC )
May 2011 Altera Corporation
V
CCIO
V
SS
CO
variation
Glossary