DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 374
DK-DEV-5SGXEA7/ES
Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-DEV-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
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1–2
Stratix V Device Handbook Volume 3: Transceivers
Figure 1–1. Basic Layout of Transceivers in Stratix V GX Devices
The location of the transceiver bank boundaries are important for clocking resources,
bonding channels, and fitting. The transceivers are grouped in transceiver blocks of
three and six channels.
example, a 5SGSB7 device has 27 transceiver channels on one side of the device, while
a 5SGXA3 device has 18 transceiver channels on each side of the device, for a total of
36 channels. Some package variations reduce the transceiver count in
Figure
1–4.
Stratix V GX Device
Figure 1–2
to
Figure 1–5
Chapter 1: Transceiver Architecture in Stratix V Devices
show the location of the blocks. For
May 2011 Altera Corporation
Hard PCS
Hard PCS
Hard PCS
Hard PCS
Hard PCS
Figure 1–3
Transceiver
Transceiver
Transceiver
Transceiver
Transceiver
PMA
PMA
PMA
PMA
PMA
and
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