DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 236

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

6–22
Fractional PLLs and Stratix V Clocking
Figure 6–21. Fractional PLL Locations for High-Speed Differential I/Os with DPA Locations Stratix V Devices
Source-Synchronous Timing Budget
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
f
1
The Stratix V device family supports fractional PLLs on each side of the device.
Figure 6–21
differential I/O receiver and transmitter channels to generate the parallel clocks
(rx_outclock and tx_outclock) and high-speed clocks (diffioclk).
For more information about fractional PLLs, refer to the
Stratix V Devices
The LVDS receiver and driver channels can be driven by the center or corner
fractional PLLs. The clock tree network cannot crossover for different I/O regions. For
example, the top left corner fractional PLL can not crossover to drive the LVDS
receiver and driver channels on the top right I/O bank when the top center fractional
PLL is driving any of the LVDS receiver and driver channels on the top left I/O bank.
For more information on the fractional PLL clocking restrictions, refer to the
“Differential Pin Placement Guidelines” on page
This section describes the timing budget, waveforms, and specifications for
source-synchronous signaling in the Stratix V device family. LVDS I/O standards
enable high-speed data transmission. This high data transmission rate results in better
overall system performance. To take advantage of fast system performance, you must
understand how to analyze timing for these high-speed signals. Timing analysis for
the differential block is different from traditional synchronous timing analysis
techniques.
General Purpose
I/O and High-Speed
LVDS I/O with
DPA and Soft CDR
Transceiver
Block
Fractional PLL
shows the location of the fractional PLLs supported for the high-speed
chapter.
Chapter 6: High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
Left Clock Region
Left Clock Region
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
FPGA Fabric
6–29.
Right Clock Region
Right Clock Region
Clock Network and PLLs in
Fractional PLLs and Stratix V Clocking
May 2011 Altera Corporation