DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 177

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
SV51006-1.3
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
May 2011
May 2011
SV51006-1.3
This chapter describes how Stratix
to work in compliance with current and emerging I/O standards and requirements.
With these device features, you can reduce board design interface costs and increase
development flexibility.
Stratix V I/Os are specifically designed for ease-of-use and rapid system integration,
while simultaneously providing the high bandwidth required to maximize internal
logic capabilities and enhance system-level performance.
The I/O capability of the Stratix V device family exceeds the I/O bandwidth available
in previous generation FPGAs. Independent modular I/O banks with a common bank
structure for vertical migration lend efficiency and flexibility to the high-speed I/Os.
Package and die enhancements with dynamic termination and output control provide
the best signal integrity in its class. Stratix V devices provide I/O features that assist
high-speed data transfer into and out of the device, including the following features:
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Up to 1020 general purpose I/Os (GPIOs) and 255 full-duplex true LVDS channels
True LVDS channels in all I/O banks support SGMII, SPI-4.2, and XSBI
applications
Hard dynamic phase alignment (DPA) and serializer/deserializer (SERDES)
support in I/O banks on all sides of the device with DPA
Single-ended, non-voltage-referenced, and voltage-referenced I/O standards
LVDS, RSDS, mini-LVDS, HSTL, SSTL, and HSUL I/O standards across all I/O
banks
Double data rate (DDR), single data rate (SDR), and half data rate input and
output options
Ubiquitous I/O support for both row and column I/Os
Deskew, read and write leveling, and clock-domain crossing functionality for
high-performance memory interface
Programmable output current strength
Programmable slew rate
Programmable input and output delays
Programmable bus-hold circuits
Programmable pull-up resistors
Open-drain output
Dynamic on-chip termination (OCT) for on-chip series (R
calibration, and on-chip parallel (R
Differential (R
D
) OCT without calibration
5. I/O Features in Stratix V Devices

V devices provide I/O capabilities that allow you
T
) termination with calibration
S
) with and without
Subscribe