DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 305

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Active Serial Configuration (Serial Configuration Devices)
Figure 9–12. Connection Setup for Programming the EPCQ Device Using the JTAG Interface
Notes to
(1) Connect the pull-up resistors to V
(2) Resistor value can vary from 1 k
(3) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect the MSEL, refer to
(4) Instantiate SFL in your design to form a bridge between the EPCS device and the Stratix V device. For more information about SFL, refer to
(5) You can use the CLKUSR pin to supply the external clock source to drive the DCLK during configuration. The maximum frequency specification
May 2011 Altera Corporation
is 100 MHz.
AN 370: Using the Serial Flash Loader with the Quartus II
Figure
9–12:
EPCQ Device
DATA0
DATA1
DATA2
DATA3
Figure 9–12
the JTAG interface.
DCLK
nCS
V

CCPGM (1)
CCPGM
to 10 k
10 kΩ
shows the connection setup when programming the EPCQ device using
and V

V
. Perform signal integrity analysis to select the resistor value for your setup.
CCPGM (1)
CCPD
10 kΩ
at a 3.0-V supply.
GND
V
CCPGM (1)
Software.
10 kΩ
AS_DATA0/ASDO
AS_DATA1
AS_DATA2
AS_DATA3
DCLK
nCSO
nSTATUS
CONF_DONE
nCONFIG
nCE
Stratix V Device
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
MSEL[4..0]
CLKUSR
Loader
Serial
Flash
(4)
TDO
TMS
TCK
TDI
V
(2)
CCPD (1)
(3)
(5)
V
CCPD (1)
1 kΩ
(2)
GND
(JTAG Mode) (Top View)
Pin 1
10-Pin Male Header
Download Cable
V
Table 9–4 on page
CCPD (1)
GND
9–7.
9–25