DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 339

no-image

DK-DEV-5SGXEA7/ES

Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Datasheets

Specifications of DK-DEV-5SGXEA7/ES

Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
SV51011-1.2
Error Detection Fundamentals
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
May 2011
May 2011
SV51011-1.2
1
This chapter describes how to activate and use the error detection cyclic redundancy
check (CRC) feature when your Stratix
from configuration errors caused by CRC errors. The error detection feature is
enhanced in the Stratix V devices.
This chapter contains the following sections:
In critical applications such as avionics, telecommunications, system control, and
military applications, it is important to be able to do the following:
For Stratix V devices, the error detection CRC feature is provided in the Quartus
software starting with version 10.0.
Using the error detection CRC feature for the Stratix V device family has no impact on
fitting or performance.
Error detection determines if the data received through a medium is corrupted during
transmission. To accomplish this, the transmitter uses a function to calculate a
checksum value for the data and appends the checksum to the original data frame.
The receiver uses the function to calculate a checksum for the received data frame and
compares the received checksum to the transmitted checksum. If the two checksum
values are equal, the received data frame is correct and no data corruption occurred
during transmission or storage.
The error detection CRC feature uses the same concept. When Stratix V devices are
successfully configured and in user mode, the error detection CRC feature ensures the
integrity of the configuration data.
“Error Detection Fundamentals” on page 10–1
“Configuration Error Detection” on page 10–2
“User Mode Error Detection and Correction” on page 10–2
“Error Detection Pin Description” on page 10–5
“Error Detection Block” on page 10–6
“Error Detection Timing” on page 10–8
“Software Support” on page 10–11
“Recovering From CRC Errors” on page 10–11
Confirm that the configuration data stored in a Stratix V device is correct.
Alert the system to the occurrence of a configuration error.
10. SEU Mitigation in Stratix V Devices
®
V device is in user mode and how to recover
Subscribe
®
II

Related parts for DK-DEV-5SGXEA7/ES