DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 524

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

6–2
Figure 6–1. Serial Loopback Datapath
PCIe Reverse Parallel Loopback
Stratix V Device Handbook Volume 3: Transceivers
Fabric
FPGA
f
1
1
When moving into or out of serial loopback, you must assert rx_digitalreset for a
minimum of two parallel clock cycles.
PCIe reverse parallel loopback is only available in the PCIe configuration for Gen1
and Gen2 data rates. As shown in
the receiver CDR, deserializer, word aligner, and rate matching FIFO buffer. It is then
looped back to the transmitter serializer and transmitted out through the
tx_serial_data port. The received data is also available to the FPGA fabric through
the rx_parallel_data signal. This loopback configuration is designed for the PCIe
specification 2.0. To enable this loopback configuration, assert the
tx_detectrxloopback signal.
This is the only loopback option supported in the PCIe configuration.
For more information, refer to the “PCI Express Reverse Parallel Loopback” section in
the
Transceiver Protocol Configuration in Stratix V Devices
Transmitter PCS
Receiver PCS
Figure
Chapter 6: Transceiver Loopback Support in Stratix V Devices
6–2, the received serial data passes through
chapter.
Transmitter PMA
Receiver PMA
PCIe Reverse Parallel Loopback
May 2011 Altera Corporation
can be Dynamically
Serial Loopback
Enabled