DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 491

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
GIGE
Figure 4–25. Rate Match Insertion in GIGE Mode
Figure 4–26. GIGE Mode Datapath with Rate Matching Enabled
May 2011 Altera Corporation
rx_coreclk
tx_coreclk
tx_clkout
rx_clkout
Fabric
FPGA
CMU PLL
(From the ×1 Clock Lines)
Transceiver Clocking and Channel Placement Guidelines
rx_rmfifodatainserted
Serial Clock
dataout
datain
Figure 4–25
symbol is required to be inserted. Because the rate match FIFO can only delete /I2/
ordered set, it inserts one /I2/ ordered set (two symbols inserted).
This section describes the transceiver clocking and placement guidelines for the GIGE
protocol supported in Stratix V devices.
Transceiver Clocking
Figure 4–26
configured for GIGE.
Central/ Local Clock Divider
Dx.y
Dx.y
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
shows an example of rate match FIFO insertion in the case where one
shows the transceiver clocking with rate matching enabled when
First /I2/ Ordered Set
K28.5
K28.5
/2
Transmitter PCS
/2
Receiver PCS
Clock Divider
D16.2
D16.2
Second /I2/ Ordered Set
K28.5
K28.5
Parallel and Serial Clocks
(Only from the Central Clock Divider)
D16.2
D16.2
Stratix V Device Handbook Volume 3: Transceivers
K28.5
D16.2
Parallel Clock
Serial Clock
Parallel and Serial Clock
Transmitter PMA
Receiver PMA
Dx.y
4–35