DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 398

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–26
Stratix V Device Handbook Volume 3: Transceivers
Byte Deserializer
The FPGA fabric-transceiver interface frequency has an upper limit. In configurations
that have a receiver PCS frequency greater than the upper limit stated, the parallel
received data and status signals cannot be forwarded directly to the FPGA fabric
because it violates this upper limit for the FPGA fabric-transceiver interface
frequency. In such configurations, the byte deserializer is required to reduce the FPGA
fabric-transceiver interface frequency to half while doubling the parallel data width.
The byte deserializer is required in configurations that exceed the FPGA
fabric-transceiver interface clock upper frequency limit. It is optional in
configurations that do not exceed the FPGA fabric-transceiver interface clock upper
frequency limit.
The byte deserializer operates in two modes:
■
■
Byte Deserializer in Single-Width Mode
In single-width mode, the byte deserializer receives 8-bit wide data from the 8B/10B
decoder or 10-bit wide data from the word aligner (if the 8B/10B decoder is disabled)
and deserializes it into 16- or 20-bit wide data at half the speed.
Figure 1–19
Figure 1–19. Byte Deserializer in Single-Width Mode
Byte Deserializer in Double-Width Mode
In double-width mode, the byte deserializer receives 16-bit wide data from the
8B/10B decoder or 20-bit wide data from the word aligner (if the 8B/10B decoder is
disabled) and deserializes it into 32- or 40-bit wide data at half the speed.
Figure 1–20
Figure 1–20. Byte Deserializer in Double-Width Mode
datain[7:0]
datain[9:0]
datain[15:0]
datain[19:0]
or
Single-width mode
Double-width mode
or
D1D2 D3D4 D5D6 D7D8
D1
shows the byte deserializer in single-width mode.
shows the byte deserializer in double-width mode.
D2
D3
D4
Deserializer
Deserializer
Byte
Byte
/2
/2
Chapter 1: Transceiver Architecture in Stratix V Devices
Receiver PCS Clock
Receiver PCS Clock
D2D4
D1D2
D2
D1
May 2011 Altera Corporation
Standard PCS Architecture
D7D8
D5D6
D4
D3
dataout[15:0}
dataout[19:0]
dataout[31:0}
dataout[3:0]
or
or