DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 334

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

9–54
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
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You can use the design security feature with or without the remote system upgrades
or decompression features.
The Stratix V design security feature provides the following security protection for
your designs:
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When you use compression with the design security feature, the configuration file is
first compressed and then encrypted using the Quartus II software. During
configuration, the Stratix V device first decrypts and then decompresses the
configuration file.
When you use design security with Stratix V devices in a FPP configuration scheme, it
requires a different DCLK-to-DATA[] ratio. For more information, refer to
Passive Parallel Configuration” on page
Secure operation mode for both volatile and non-volatile key through tamper
protection bit setting
JTAG secure mode is enable through tamper-protection bit
Supports board level testing
Supports in-socket key programming for non-volatile key
Available in all configuration schemes except JTAG
Supports both remote system upgrades and decompression feature
Security against copying—the security key is securely stored in the Stratix V
device and cannot be read out through any interface. In addition, as configuration
file read-back is not supported in Stratix V devices, your design information
cannot be copied.
Security against reverse engineering—reverse engineering from an encrypted
configuration file is very difficult and time consuming because the Stratix V
configuration file formats are proprietary and the file contains millions of bits that
require specific decryption. In addition, the Stratix V devices are manufactured on
the most advanced 28-nm process technology, making this process very difficult.
Security against tampering—this disables tamper attempts through the JTAG
interface. You can enhance this security feature with the tamper protection bit
setting. After the tamper protection bit is set, the Stratix V device can only accept
configuration files encrypted with the same key. Additionally, programming
through the JTAG interface is blocked. This prevents any attempts to tamper with
the device from both the JTAG interface and the configuration interface.
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
9–9.
May 2011 Altera Corporation
“Fast
Design Security