DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 434

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

2–18
Stratix V Device Handbook Volume 3: Transceivers
Bonded Channel Configurations
In bonded configurations, the receiver standard PCS requires both the parallel clock
(recovered) and parallel clock from the clock divider.
In bonded configurations, the receiver 10G PCS uses only the parallel clock
(recovered) for all its blocks.
Figure 2–15
configuration using the receiver standard PCS. The receiver PCS uses both the parallel
clock (recovered) and parallel clock from the clock divider. The parallel clock from the
clock divider is generated by the central clock divider for the transmitter PCS. It also
drives some blocks in the receiver PCS depending on the configuration you use.
shows five channels in a transceiver bank configured in bonded
Chapter 2: Transceiver Clocking in Stratix V Devices
May 2011 Altera Corporation
Internal Clocking