DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 10

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–4
Stratix V Family Plan
Stratix V Device Handbook
Table 1–1
Table 1–1. Stratix V GT Device Features
Logic Elements (K)
Registers (K)
28/12.5-Gbps Transceivers
PCIe hard IP Blocks
Fractional PLLs
M20K Memory Blocks
M20K Memory (MBits)
Variable Precision Multipliers (18×18)
Variable Precision Multipliers (27×27)
DDR3 SDRAM ×72 DIMM Interfaces
40G/100G PCS hard IP Blocks
User I/Os, Full-Duplex LVDS, 28/14.1-Gbps Transceivers
KF40-F1517
Notes to
(1) Packages are flipchip ball grid array (1.0-mm pitch).
(2) Each package row offers pin migration (common board footprint) for all devices in the row.
(3) For full package details, refer to the
(4) Migration between select Stratix V GT devices and Stratix V GX devices is available. For more information, refer to
Table 1–5 on page
Table
lists the Stratix V GT device features.
Package (1), (2),
(4)
1–1:
Features
1–9.
(3)
Package Information Datasheet for Altera
600, 150, 4/32
5SGTC5
5SGTC5
2,304
4/32
425
642
512
256
Yes
24
45
Chapter 1: Stratix V Device Family Overview
1
4
Devices.
June 2011 Altera Corporation
600, 150, 4/32
Stratix V Family Plan
5SGTC7
5SGTC7
2,560
4/32
622
939
512
256
Yes
24
50
1
4