DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 59

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: DC and Switching Characteristics for Stratix V Devices
Glossary
Table 2–36. Glossary (Part 2 of 4)
May 2011 Altera Corporation
Letter
M
K
N
O
P
Q
R
J
L
J
JTAG Timing
Specifications
PLL
Specifications
R
L
Subject
—
—
High-speed I/O block—Deserialization factor (width of parallel data bus).
JTAG Timing Specifications:
Diagram of PLL Specifications
Note:
(1) Core Clock can only be fed by dedicated clock input pins or PLL outputs.
Receiver differential input discrete resistor (external to the Stratix V device).
TMS
TDO
TCK
TDI
Core Clock
Key
CLK
4
Reconfigurable in User Mode
t
JCH
t
JPZX
t
JCP
t
JCL
Switchover
f
IN
External Feedback
N
t
JPCO
f
INPFD
(1)
t
JPSU
PFD
Definitions
Stratix V Device Handbook Volume 1: Overview and Datasheet
CP
—
—
Delta Sigma
Modulator
t
LF
JPH
VCO
f
VCO
t
JPXZ
Counters
C0..C17
CLKOUT Pins
f
f
OUT_EXT
OUT
GCLK
RCLK
2–31