DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 424
DK-DEV-5SGXEA7/ES
Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-DEV-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
- Current page: 424 of 530
- Download datasheet (16Mb)
2–8
Stratix V Device Handbook Volume 3: Transceivers
Figure 2–7
with a central clock divider of channel 1 and 4 in a transceiver bank. You can drive the
×N clock lines with the ×6 clock lines. ×6 clock lines can drive any channel within a
transceiver bank. The ×N clock lines span the entire side of the device and can directly
drive any channel within or outside a transceiver bank.
shows both ×6 and ×N clock lines. You can only drive the ×6 clock lines
Chapter 2: Transceiver Clocking in Stratix V Devices
May 2011 Altera Corporation
Internal Clocking
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