DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 316

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

9–36
Figure 9–22. JTAG Configuration of a Single Device Using a Microprocessor
Notes to
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all Stratix V devices in the chain. V
(2) If you only use the JTAG configuration, connect nCONFIG to V
(3) Connect nCE to GND or drive it low for successful JTAG configuration.
(4) The microprocessor must use the same I/O standard as V
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
to meet the V
convenient on your board. If you are using JTAG in conjunction with another configuration scheme, set the MSEL[4..0] and tie nCONFIG and
DCLK based on the selected configuration scheme.
Figure
CONFIG_IO Instruction
Multi-Device JTAG Configuration
9–22:
IH
1
specification of the I/O on the device.
Microprocessor
Figure 9–22
The CONFIG_IO instruction allows you to configure I/O buffers using the JTAG port
and when issued, interrupts configuration. This instruction allows you to perform
board-level testing prior to configuring the Stratix V device or waiting for a
configuration device to complete configuration. After configuration is interrupted
and JTAG testing is complete, you must reconfigure the part using the JTAG interface
or if you support FPP, PS, or AS on your board, reconfigure the device by externally
pulsing nCONFIG low. Alternatively, you can pulse nCONFIG low through the same
JTAG interface using the PULSE_NCONFIG JTAG instruction.
All JTAG instructions (except BYPASS, IDCODE, and SAMPLE) can be issued by first
interrupting the configuration and reprogramming the I/O pins using the
CONFIG_IO instruction.
When programming a JTAG device chain, one JTAG-compatible header is connected
to several devices. The number of devices in the JTAG chain is limited only by the
drive capability of the download cable. When four or more devices are connected in a
JTAG chain, Altera recommends buffering the TCK, TDI, and TMS pins with an
on-board buffer. You can place other Altera devices that have JTAG support in the
same JTAG chain for device programming.
ADDR
Memory
DATA
shows a JTAG configuration of a Stratix V device using a microprocessor.
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
CCPD
to drive the JTAG pins.
CCPGM
V
CCPD
and MSEL[4..0] to GND. Pull DCLK either high or low, whichever is
TRST
TDI (4)
TCK (4)
TMS (4)
TDO (4)
Stratix V Device
CONF_DONE
MSEL[4..0]
nCONFIG
nSTATUS
DCLK
nCEO
nCE
N.C.
GND
(2)
(2)
(2)
V
10 k
CCPGM(1)
10 k
May 2011 Altera Corporation
V
CCPGM
CCPGM(1)
must be high enough
JTAG Configuration