DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 285

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Configuration Sequence
May 2011 Altera Corporation
Configuration Error
Initialization
1
1
After the Stratix V device has received all the configuration data successfully, it
releases the CONF_DONE pin, which is pulled high by a pull-up resistor. A low-to-high
transition on CONF_DONE indicates configuration has completed and initialization of
the device can begin. For the FPP and PS schemes, DCLK must not be left floating at the
end of configuration. You must drive them either high or low, whichever is
convenient on your board.
For the FPP and PS schemes, there is no maximum DCLK period, which means you can
stop the configuration by holding the DCLK low for an indefinite amount of time. To
resume configuration, the external host must provide data on the DATA[] pins prior to
sending the first DCLK rising edge.
If the Auto-restart configuration after error option (available in the Quartus
software from the General panel of the Device and Pin Options dialog box) is turned
on, the Stratix V device releases the nSTATUS pin high after the specified time indicated
by tSTATUS and retries the configuration. If this option is turned off or if you are using
a PS or FPP scheme with an external controller, the system must monitor the nSTATUS
for errors and sends a low-to-high signal on nCONFIG for specified t
the configuration.
In Stratix V devices, initialization begins after the CONF_DONE goes high. For the FPP
and PS configuration schemes, two DCLK falling edges are required after the last
configuration byte is sent to the Stratix V device to begin the initialization of the
device for both uncompressed and compressed configuration data.
The initialization clock source is from the internal oscillator, CLKUSR, or DCLK pin. By
default, the internal oscillator is the clock source for initialization. If you use the
internal oscillator, the Stratix V device provides itself with enough clock cycles for
proper initialization.
Table 9–3
schemes, and the maximum frequency.
Table 9–3. Initialization Clock Source Option and the Maximum Frequency
If you use the optional CLKUSR pin as the initialization clock source and nCONFIG is
pulled low to restart configuration during device initialization, ensure that CLKUSR or
DCLK continues toggling until nSTATUS goes low and goes high again.
Internal Oscillator
CLKUSR
Notes to
(1) The minimum number of clock cycles required for device initialization.
(2) To enable CLKUSR as the initialization clock source, turn on the Enable user-supplied start-up clock (CLKUSR)
(3) The number is still preliminary.
Initialization Clock
option in the Quartus II software from the General panel of the Device and Pin Options dialog box.
Source
Table
lists the initialization clock source option, the applicable configuration
9–3:
Configuration Schemes
AS, PS, FPP
AS, PS, FPP
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
(2)
Frequency
Maximum
12.5 MHz
125 MHz
Minimum Number of Clock
CFG
Cycles
17,408
time to restart
(3)
(1)
®
II
9–5