DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 81

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Logic Array Blocks and Adaptive Logic Modules in Stratix V Devices
Logic Array Blocks
Figure 1–3. Direct-Link Connection
May 2011 Altera Corporation
Direct-link
interconnect
to left
LAB Interconnects
LAB Control Signals
Direct-link interconnect from the
block, DSP block, or IOE output
left LAB, MLAB/M20K memory
ALMs
The LAB local interconnect can drive ALMs in the same LAB. It is driven by column
and row interconnects and ALM outputs in the same LAB. Neighboring
LABs/MLABs, M20K blocks, or digital signal processing (DSP) blocks from the left or
right can also drive the LAB’s local interconnect through the direct link connection.
The direct link connection feature minimizes the use of row and column
interconnects, providing higher performance and flexibility. Each LAB can drive
30 ALMs through fast-local and direct-link interconnects.
Figure 1–3
Each LAB contains dedicated logic for driving control signals to its ALMs. The control
signals include three clocks, three clock enables, two asynchronous clears, a
synchronous clear, and a synchronous load, for a maximum of 10 control signals at a
time. Although you generally use synchronous load and clear signals when
implementing counters, you can also use them with other functions.
Each LAB has two unique clock sources and three clock enable signals, as shown in
Figure
sources and three clock enable signals. Each LAB’s clock and clock enable signals are
linked. For example, any ALM in a particular LAB using the labclk1 signal also uses
the labclkena1 signal. If the LAB uses both the rising and falling edges of a clock, it
also uses two LAB-wide clock signals. Deasserting the clock enable signal turns off the
corresponding LAB-wide clock.
1–4. The LAB control block can generate up to three clocks using two clock
MLAB
shows the direct-link connection.
Interconnect
Local
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
LAB
ALMs
Direct-link
interconnect
to right
Direct-link interconnect from the
right LAB, MLAB/M20K memory
block, DSP block, or IOE output
1–3