DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 46

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: DC and Switching Characteristics for Stratix V Devices
Switching Characteristics
Table 2–21. PLL Specifications for Stratix V Devices (Part 2 of 3)—Preliminary
May 2011 Altera Corporation
t
f
t
t
f
t
t
t
t
t
t
t
t
f
dK
k
CONFIGPHASE
DYCONFIGCLK
LOCK
DLOCK
CLBW
PLL_PSERR
ARESET
INCCJ
OUTPJ_DC
OUTCCJ_DC
OUTPJ_IO
(9)
OUTCCJ_IO
(9)
CASC_OUTPJ_DC
(6),
DRIFT
VALUE
BIT
Symbol
(7)
(4),
(6),
(6)
(6),
(6)
(5)
Time required to reconfigure phase shift
Dynamic Configuration Clock
Time required to lock from the end-of-device configuration
or de-assertion of areset
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
PLL closed-loop low bandwidth
PLL closed-loop medium bandwidth
PLL closed-loop high bandwidth
Accuracy of PLL phase shift
Minimum pulse width on the areset signal
Input clock cycle-to-cycle jitter (F
Input clock cycle-to-cycle jitter (F
Period Jitter for dedicated clock output (F
Period Jitter for dedicated clock output (F
Cycle-to-Cycle Jitter for a dedicated clock output
(F
Cycle-to-Cycle Jitter for a dedicated clock output
(F
Period Jitter for a clock output on a regular I/O
(F
Period Jitter for a clock output on a regular I/O
(F
Cycle-to-Cycle Jitter for a clock output on a regular I/O
(F
Cycle-to-Cycle Jitter for a clock output on a regular I/O
(F
Period Jitter for a dedicated clock output in cascaded PLLs
(F
Period Jitter for a dedicated clock output in cascaded PLLs
(F
Frequency drift after PFDENA is disabled for a duration of
100 µs
Bit number of Delta Sigma Modulator (DSM)
Numerator of Fraction
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
≥ 100 MHz)
≥ 100 MHz)
< 100 MHz)
< 100 MHz)
≥ 100 MHz)
< 100 MHz)
< 100 MHz)
≥ 100 MHz)
Parameter
REF
REF
(8)
< 100 MHz)
≥ 100 MHz)
OUT
OUT
≥ 100 MHz)
< 100 MHz)
Stratix V Device Handbook Volume 1: Overview and Datasheet
–750
Min
—
—
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(Note 1)
8388608
TBD
0.15
Typ
0.3
1.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
24
4
(1)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
+750
Max
100
±50
±10
—
—
—
—
—
—
—
—
1
1
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
mUI (p-p)
mUI (p-p)
mUI (p-p)
mUI (p-p)
mUI (p-p)
UI (p-p)
ps (p-p)
ps (p-p)
ps (p-p)
ps (p-p)
ps (p-p)
ps (p-p)
MHz
MHz
MHz
MHz
Unit
Bits
ms
ms
—
ps
—
ns
%
2–18