DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 24

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–18
Table 1–12. Configuration Modes for Stratix V Devices
Stratix V Device Handbook
Active Serial
Passive Serial
Passive Parallel
Configuration via
Protocol
Partial
Reconfiguration
JTAG
Note to
(1) Remote update support with the Parallel Flash Loader.
Mode
Table
Partial Reconfiguration
1–12:
Slow POR
Fast or
easier to achieve when only the PCIe hard IP and periphery are loaded. After the PCIe
hard IP and periphery are loaded and the root port is booted up, application software
running on the root port can send the configuration file for the FPGA fabric across the
PCIe link where it is loaded into the FPGA. The FPGA is then fully configured and
functional.
Table 1–12
Partial reconfiguration allows you to reconfigure part of the FPGA while other
sections continue to operate. This is required in systems where uptime is critical
because it allows you to make updates or adjust functionality without disrupting
services. While lowering power and cost, partial reconfiguration also increases the
effective logic density by removing the necessity to place the FPGA functions that do
not operate simultaneously. Instead, these functions can be stored in external memory
and loaded as required. This reduces the size of the FPGA by allowing multiple
applications on a single FPGA, saving board space and reducing power.
Up to now, partial reconfiguration solutions have been time-intensive tasks that
required you to know all of the intricate FPGA architecture details. Altera simplifies
the partial reconfiguration process by building the capability on top of the proven
incremental compilation design flow in its Quartus II design software.
Partial reconfiguration is supported through the following configuration options:
■
■
■
v
v
v
—
—
—
Partial reconfiguration through the FPP ×16 I/O interface
Configuration via Protocol
Soft internal core, such as the Nios
Compression
lists the available configuration modes for Stratix V devices.
v
v
v
—
—
—
Encryption
v
v
v
v
v
—
Remote
Update
®
v
—
v
v
—
(1)
II processor.
Enhanced Configuration and Configuration via Protocol
Data Width
8, 16, 32
1, 2, 4, 8
1, 4
16
1
1
Chapter 1: Stratix V Device Family Overview
Max Clock
Rate (MHz)
100
125
125
125
June 2011 Altera Corporation
—
33
Max Data Rate
(Mbps)
3,000
3,000
2,000
400
125
33