DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 306

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

9–26
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Figure 9–13
the AS interface.
Figure 9–13. Connection Setup for Programming the EPCS Device Using the AS Interface
Notes to
(1) Connect the pull-up resistors to V
(2) Power up the USB-ByteBlaster, ByteBlaster II, or EthernetBlaster cable's V
(3) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect the MSEL, refer
(4) You can use the CLKUSR pin to supply the external clock source to drive the DCLK during configuration. The
to
maximum frequency specification is 100 MHz.
Table 9–4 on page
Figure
shows the connection setup when programming the EPCS device using
9–13:
EPCS Device
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
9–7.
DATA
DCLK
ASDI
nCS
V
CCPGM (1)
10 kΩ
CCPGM
and V
10 kΩ
USB-Blaster or ByteBlaser II
V
CCPGM (1)
10-Pin Male Header
CCPD
Pin 1
(AS Mode)
at a 3.0-V supply.
10 kΩ
V
V
10 kΩ
CCPGM (2)
Active Serial Configuration (Serial Configuration Devices)
CCPGM (1)
CONF_DONE
nSTATUS
nCONFIG
nCE
AS_DATA1
DCLK
nCSO
ASDO
GND
Stratic V Device
CC(TRGT)
MSEL[4..0]
CLKUSR
with V
nCEO
May 2011 Altera Corporation
CCPGM
.
N.C.
(3)
(4)