DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 425

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: Transceiver Clocking in Stratix V Devices
Internal Clocking
May 2011 Altera Corporation
1
Figure 2–7. ×6 and ×N Clock Lines Used for Bonded Configurations
Note to
(1) The clock lines carry both serial and parallel clocks.
The ×N clock lines are currently only supported for PCIe ×8 Gen1 and Gen2
configurations.
Transceiver Bank
Transceiver Bank
Figure
2–7:
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Central Clock
Central Clock
Central Clock
Central Clock
Local Clock
Local Clock
Local Clock
Local Clock
Local Clock
Local Clock
Local Clock
Local Clock
Divider
Divider
Divider
Divider
Divider
Divider
Divider
Divider
Divider
Divider
Divider
Divider
Stratix V Device Handbook Volume 3: Transceivers
×6 Clock Lines (1)
×6 Clock Lines (1)
Clock Line (1)
×N_bottom
Clock Line (1)
×N_top
2–9