DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 90

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–12
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Figure 1–11
Figure 1–11. ALM in Shared Arithmetic Mode
You can find adder trees in many different applications. For example, you can
implement the summation of the partial products in a logic-based multiplier in a tree
structure. Another example is a correlator function that can use a large adder tree to
sum filtered data samples in a given time frame to recover or despread data that was
transmitted using spread-spectrum technology.
Shared Arithmetic Chain
The shared arithmetic chain available in enhanced arithmetic mode allows the ALM
to implement a three-input add. This significantly reduces the resources necessary to
implement large adder trees or correlator functions.
The shared arithmetic chains can begin in either the first or sixth ALM in the LAB. The
Quartus II Compiler creates shared arithmetic chains longer than 20 (10 ALMs in
arithmetic or shared arithmetic mode) by linking LABs together automatically. For
enhanced fitting, a long shared arithmetic chain runs vertically, allowing fast
horizontal connections to the MLAB/M20K memory and DSP blocks. A shared
arithmetic chain can continue as far as a full column.
Similar to carry chains, the top and bottom halves of shared arithmetic chains in
alternate LAB columns can be bypassed. This capability allows the shared arithmetic
chain to cascade through half of the ALMs in a LAB while leaving the other half
available for narrower fan-in functionality. The top half of every other LAB column
can be bypassed, while the bottom half of the other LAB columns can be bypassed.
For more information on shared arithmetic chain interconnect, refer to
Interconnects” on page
shows the ALM using this feature.
datae0
datae1
datac
datab
dataa
datad
1–14.
Chapter 1: Logic Array Blocks and Adaptive Logic Modules in Stratix V Devices
4-Input
4-Input
4-Input
4-Input
LUT
LUT
LUT
LUT
shared_arith_out
shared_arith_in
carry_in
carry_out
labclk
D
D
D
D
reg0
reg1
reg2
reg3
Q
Q
Q
Q
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local routing
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May 2011 Altera Corporation
Adaptive Logic Modules
“ALM