DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 52

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: DC and Switching Characteristics for Stratix V Devices
Switching Characteristics
Table 2–27. DPA Lock Time Specifications for Stratix V GX Devices Only—Preliminary
May 2011 Altera Corporation
SPI-4
Parallel Rapid I/O
Miscellaneous
Notes to
(1) The DPA lock time is for one channel.
(2) One data transition is defined as a 0-to-1 or 1-to-0 transition.
(3) The DPA lock time stated in this table applies to both commercial and industrial grade.
(4) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
Standard
Table
2–27:
Figure 2–1
the DPA PLL calibration option enabled.
Figure 2–1. DPA Lock Time Specification with DPA PLL Calibration Enabled
Table 2–27
00000000001111111111
rx_dpa_locked
Training Pattern
rx_reset
00001111
10010000
10101010
01010101
shows the dynamic phase alignment (DPA) lock time specifications with
lists the DPA lock time specifications for Stratix V GX devices.
transitions
256 data
Transitions in One
Repetition of the
Training Pattern
Number of Data
2
2
4
8
8
clock cycles
96 slow
Stratix V Device Handbook Volume 1: Overview and Datasheet
DPA Lock Time
transitions
Data Transitions
Repetitions per 256
256 data
Number of
128
128
64
32
32
clock cycles
96 slow
(Note
(4)
1), (2),
transitions
640 data transitions
640 data transitions
640 data transitions
640 data transitions
640 data transitions
256 data
(3)
Maximum
2–24