DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 495

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
XAUI
May 2011 Altera Corporation
Transceiver Datapath in a XAUI Configuration
Figure 4–29
the XAUI PCS is implemented in soft logic inside the FPGA core when using the
XAUI PHY IP core. In future versions of the Quartus II software, a hard XAUI PCS
will be supported. If you plan on migrating to the hard XAUI PCS in the future, you
must ensure that your channel placement is compatible between the soft and hard
PCS implementations. For placement guidelines, refer to
Placement Guidelines” on page
Figure 4–29. Stratix V XAUI Configuration
Note to
(1) Implemented in soft logic.
Figure
4–29:
shows the transceiver blocks enabled in a XAUI configuration. Currently,
Transceiver PHY IP
Lane Data Rate
Number of Bonded Channels
Word Aligner (Pattern Length) (1)
8B/10B Encoder/Decoder (1)
Deskew FIFO (1)
Rate Match FIFO (1)
Byte SERDES
Byte Ordering
FPGA Fabric-to-Transceiver
Interface Width
FPGA Fabric-to-Transceiver
Interface Frequency
4–44.
Stratix V Device Handbook Volume 3: Transceivers
“Transceiver Channel
XAUI PHY IP
10-Bit/K28.5
156.25 MHz
3.125 Gbps
Disabled
Enabled
Enabled
Enabled
Enabled
16-Bit
×4
4–39