DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 459

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
10GBASE-R
Figure 4–2. Transceiver Blocks Enabled in 10GBASE-R
May 2011 Altera Corporation
Transceiver Datapath Configuration
Transceiver PHY IP
Lane Data Rate
Number of Bonded Channels
PCS-PMA Interface Width
Gear Box
Block Synchronizer
Disparity Generator/Checker
Scrambler, Descrambler (Mode)
64B/66B Encoder/Decoder
BER Monitor
Frame Generator, Synchronizer
RX FIFO (Mode)
TX FIFO (Mode)
FPGA Fabric-to-Transceiver
Interface Width
FPGA Fabric-to-Transceiver
Interface Frequency
CRC32 Generator, Checker
Figure 4–2
configuration. The blocks shown as “Disabled” are not used, but incur latency. The
blocks shown as “Bypassed” are not used and do not incur any latency.
shows the transceiver blocks and settings enabled in a 10GBASE-R
(Phase Compensation Mode)
(Clock Compensation Mode)
(Self Synchronous Mode)
10GBASE-R PHY IP
10.3125 Gbps
Bypassed
8-bit Control
156.25 MHz
Bypassed
Bypassed
64-bit Data
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
40-Bit
None
Stratix V Device Handbook Volume 3: Transceivers
4–3