DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 156
DK-DEV-5SGXEA7/ES
Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-DEV-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
- Current page: 156 of 530
- Download datasheet (16Mb)
4–16
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Clock Enable Signals
You can enable or disable the dedicated external clock output pins using the
ALTCLKCTRL megafunction.
control block.
Figure 4–12. External PLL Output Clock Control Block for Stratix V Devices
Notes to
(1) When the device is in user mode, you can only set the clock select signals through a configuration file (.sof or .pof);
(2) The clock control block feeds to a multiplexer within the FPLL_<#>_CLKOUT pin’s IOE. The FPLL_<#>_CLKOUT
Figure 4–13
is implemented in Stratix V devices.
Figure 4–13. clkena Implementation
Notes to
(1) The R1 and R2 bypass paths are not available for the PLL external clock outputs.
(2) The select line is statically controlled by a bit setting in the configuration file (.sof or .pof).
they cannot be dynamically controlled.
pin is a dual-purpose pin. Therefore, this multiplexer selects either an internal signal or the output of the clock control
block.
output of clock
Figure
Figure
select mux
shows how the clock enable and disable circuit of the clock control block
clkena
4–12:
4–13:
D
(1)
R1
Q
IOE
Internal
FPLL_<#>_CLKOUT pin
Logic
(2)
Figure 4–12
D
R2
PLL Counter
(1)
Q
Outputs
18
Enable/
Disable
shows the external PLL output clock
Chapter 4: Clock Networks and PLLs in Stratix V Devices
Internal
Static Clock
Select (1)
Logic
Static Clock Select
(2)
(1)
Clock Networks in Stratix V Devices
GCLK/
RCLK/
FPLL_<#>_CLKOUT (1)
May 2011 Altera Corporation
Related parts for DK-DEV-5SGXEA7/ES
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV STRATIX IV FPGA 4SE530
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV FPGA 2AGX260 W/6.375G TX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV MAX V 5M570Z
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX III
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV ARRIA GX 1AGX60N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT STARTER CYCLONE IV GX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: