DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 20

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–14
Adaptive Logic Module
Clocking
Fractional PLL
Stratix V Device Handbook
Stratix V devices use an improved ALM to implement logic functions more efficiently.
The Stratix V ALM has eight inputs with a fracturable look-up table (LUT), two
dedicated embedded adders, and four dedicated registers.
The Stratix V ALM has the following enhancements:
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The Quartus II software leverages the Stratix V ALM logic structure to deliver the
highest performance, optimal logic usage, and lowest compile times. The Quartus II
software simplifies design re-use because it automatically maps legacy Stratix designs
into the new Stratix V ALM architecture.
The Stratix V device core clock network is designed to support 717-MHz fabric
operations and 1,066-MHz/1,600-Mbps external memory interfaces. The clock
network architecture is based on Altera’s proven global, quadrant, and peripheral
clock structure, which is supported by dedicated clock input pins and fractional clock
synthesis PLLs. The Quartus II software identifies all unused sections of the clock
network and powers them down, which reduces power consumption.
Stratix V devices have up to 32 fractional PLLs that you can use to reduce both the
number of oscillators required on the board and the clock pins used in the FPGA by
synthesizing multiple clock frequencies from a single reference clock source. In
addition, you can use the fractional PLLs for clock network delay compensation,
zero-delay buffering, and transmit clocking for transceivers. Fractional PLLs may be
individually configured for integer mode or fractional mode with third-order
delta-sigma modulation.
Packs 6% more logic when compared with the ALM found in Stratix IV devices
Implements select 7-input LUT-based functions, all 6-input logic functions, and
two independent functions consisting of smaller LUT sizes (such as two
independent 4-input LUTs) to optimize core usage
Adds more registers (four registers per 8-input fracturable LUT). This allows
Stratix V devices to maximize core performance at a higher core logic usage and
provides easier timing closure for register-rich and heavily pipelined designs.
Chapter 1: Stratix V Device Family Overview
June 2011 Altera Corporation
Adaptive Logic Module