DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 433

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: Transceiver Clocking in Stratix V Devices
Internal Clocking
May 2011 Altera Corporation
f
Figure 2–14
receiver standard PCS that do not use a rate match FIFO. The CDR of each channel
recovers the serial clock (recovered) from the incoming data and generates the parallel
clock (recovered) by dividing the serial clock (recovered). Depending on the
configuration, the receiver PCS may also use the parallel clock from the clock divider
that is generated by the local clock divider for the transmitter.
Figure 2–14. Three Channels Configured in Non-Bonded Configuration
For more information about the clocking scheme used in different configurations,
refer to the
Custom Configurations in Stratix V Devices
Ch5
Ch4
Ch3
CMU PLL
CMU PLL
CMU PLL
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Transceiver Protocol Configurations in Stratix V Devices
shows three channels, configured in non-bonded configuration, using the
Local Clock Divider
Central Clock Divider
Local Clock Divider
Receiver PCS
Receiver PCS
Receiver PCS
Clock Divider
Clock Divider
Clock Divider
chapters.
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Stratix V Device Handbook Volume 3: Transceivers
To the Transmitter Channel
To the Transmitter Channel
To the Transmitter Channel
Receiver PMA
Receiver PMA
Receiver PMA
Reference
Reference
Reference
Clock
Clock
Clock
and
Input
Input
Input
Transceiver
×1 Clock Lines
2–17