DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 523

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

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SV52007-2.0
Serial Loopback
Stratix V Device Handbook Volume 3: Transceivers
May 2011
May 2011
SV52007-2.0
This chapter describes the loopback options used on Stratix
which allow you to verify how different functional blocks work in the transceiver
standard physical coding sublayer (PCS).
The four available standard PCS loopback options are:
■
■
■
■
Serial loopback is available for all configurations except the PCIe configuration.
Figure 6–1
passes through the transmitter channel and is looped back to the receiver channel,
bypassing the receiver buffer. The received data is available to the FPGA logic for
verification. With this option, you can review how the enabled PCS and physical
media attachment (PMA) functional blocks in the transmitter and receiver channel
work. Furthermore, you can dynamically enable serial loopback on a
channel-by-channel basis.
When you enable serial loopback, the transmitter channel sends the data to both the
tx_serial_data output port and to the receiver channel. The differential output
voltage on the tx_serial_data ports is based on the selected differential output
voltage (V
recovery (CDR) and is retimed through different clock domains. You must provide an
alignment pattern for the word aligner to enable the receiver channel to retrieve the
byte boundary.
If the device is not in the serial loopback configuration and is receiving data from a
remote device, the receiver CDR’s recovered clock is locked to the data from that
source. If the device is placed in the serial loopback configuration, the data source to
the receiver changes from the remote device to the local transmitter channel. This
prompts the receiver CDR to start tracking the phase of the new data source. During
this time, the receiver CDR’s recovered clock may be unstable. As the receiver PCS is
running off of this recovered clock, you must place the receiver PCS under reset by
asserting the rx_digitalreset signal during this time period.
“Serial
(PCIe
“PCIe Reverse Parallel Loopback” on page
configuration only
“Reverse Serial Loopback” on page
“Reverse Serial Pre-CDR Loopback” on page
configuration
®
) configuration
OD
Loopback”—available in all configurations except the PCI Express
shows the datapath for serial loopback. The data from the FPGA fabric
) settings. The looped back data is received by the receiver clock data
6. Transceiver Loopback Support in
6–3—supported in custom configuration
6–2—supported in the PCIe
6–4—supported in custom
Stratix V Devices
®
V GX and GS devices,
®
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