DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 148

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–8
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Clock Network Sources
f
1
In Stratix V devices, clock input pins, PLL outputs, high-speed serial interface (HSSI)
outputs, DPA outputs, and internal logic can drive the GCLK and RCLK networks.
For connectivity between the dedicated clock pins, GCLK, and RCLK networks, refer
to
Dedicated Clock Input Pins
CLK pins can be either differential clocks or single-ended clocks. Stratix V devices
support up to 28 differential clock inputs or 56 single-ended clock inputs. You can also
use dedicated clock input pins CLK[27..0] for high fan-out control signals such as
asynchronous clears, presets, and clock enables for protocol signals through the
GCLK or RCLK networks.
Internal Logic
You can drive each GCLK, RCLK, and horizontal PCLK network using LAB-routing
and row clock to enable internal logic to drive a high fan-out, low-skew signal.
Stratix V PLLs cannot be driven by internally generated GCLKs, RCLKs, or horizontal
PCLKs. The input clock to the PLL has to come from dedicated clock input pins or
pin/PLL-fed GCLKs or RCLKs.
DPA Outputs
Every DPA generates one PCLK to the core.
HSSI Outputs
Every three HSSI outputs generate a group of six PCLKs to the core.
For more information about DPA and HSSI outputs, refer to the
I/O Interfaces with DPA in Stratix V Devices
PLL Clock Outputs
Stratix V PLL clock outputs can drive both GCLK and RCLK networks.
Table 4–2
and
Table 4–3 on page
4–10.
chapter.
Chapter 4: Clock Networks and PLLs in Stratix V Devices
Clock Networks in Stratix V Devices
High-Speed Differential
May 2011 Altera Corporation