DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 337

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Design Security
May 2011 Altera Corporation
Design Security Implementation Steps
Stratix V devices are SRAM-based devices. To provide design security, Stratix V
devices require a 256-bit security key for configuration bitstream design security. To
carry out secure configuration, follow these steps:
1. The Quartus II software generates the design security key programming file and
2. Store the encrypted configuration file in the external memory.
3. Program the AES key programming file into the Stratix V device through a JTAG
4. Configure the Stratix V device. At system power-up, the external memory device
Figure 9–34
Figure 9–34. Design Security Implementation Steps
256-bit User-Defined
encrypts the configuration data using the user-defined 256-bit key.
interface.
sends the encrypted configuration file to the Stratix V device.
Key
shows the design security implementation steps.
Quartus II
Programming File
AES Encryptor
Configuration
Encrypted
AES Key
File
Step 1
Step 1
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Step 2
Step 3
Configuration
Stratix V FPGA
Memory or
Key Storage
Decryption
Device
AES
Step 4
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