DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 56

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: DC and Switching Characteristics for Stratix V Devices
I/O Timing
Table 2–32. OCT Calibration Block Specifications for Stratix V Devices—Preliminary
I/O Timing
May 2011 Altera Corporation
OCTUSRCLK
T
T
T
Note to
(1) Pending silicon characterization.
OCTCAL
OCTSHIFT
RS_RT
Symbol
Table
2–32:
f
Clock required by the OCT calibration blocks
Number of OCTUSRCLK clock cycles required for OCT R
calibration
Number of OCTUSRCLK clock cycles required for the OCT
code to shift out
Time required between the dyn_term_ctrl and oe signal
transitions in a bidirectional I/O buffer to dynamically switch
between OCT R
OCT Calibration Block Specifications
Table 2–32
Duty Cycle Distortion (DCD) Specifications
Table 2–33
Table 2–33. Worst-Case DCD on Stratix V I/O Pins—Preliminary
Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the
Quartus II Timing Analyzer.
Excel-based I/O timing provides pin timing performance for each device density and
speed grade. The data is typically used prior to designing the FPGA to get an estimate
of the timing budget as part of the link timing analysis. The Quartus II Timing
Analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after you complete place-and-route.
You can download the Excel-based I/O Timing spreadsheet from the
Devices Literature
Output Duty Cycle
Note to
(1) The numbers are preliminary pending silicon characterization.
Symbol
Table
S
and R
lists the OCT calibration block specifications for Stratix V devices.
lists the worst-case DCD for Stratix V devices.
2–33:
T
Description
webpage.
Min
–2 Speed Grade
45
Max
55
–3 Speed Grade –4 Speed Grade
Min
Stratix V Device Handbook Volume 1: Overview and Datasheet
45
S
/R
T
Max
55
Min
—
—
—
—
(Note 1)
Min
(Note 1)
45
1000
Typ
2.5
—
32
Max
55
Stratix V
Max
20
—
—
—
Unit
%
Cycles
Cycles
MHz
Unit
ns
2–28