DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 432

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

2–16
Table 2–3. Clock Sources for All Receiver PCS Blocks
Stratix V Device Handbook Volume 3: Transceivers
Note to
(1) For more information about loopback mode, refer to the
Standard
PCS
10G
Table
2–3:
Word aligner
Rate match FIFO
8B/10B decoder
Byte deserializer
Byte ordering
Receiver (RX) phase
compensation FIFO
All PCS blocks
f
Block
The CDR in the PMA of each channel recovers the serial clock from the incoming data.
The CDR also divides the serial clock (recovered) to generate the parallel clock
(recovered). Both clocks are used by the deserializer. The receiver PCS can use the
following clocks depending on the configuration of the receiver channel:
■
■
Table 2–3
receiver PCS.
Non-Bonded Channel Configurations
In non-bonded configurations, the receiver standard PCS requires both the parallel
clock (recovered) and parallel clock from the clock divider. Depending on the
configuration, it may require the parallel clock from the clock divider that is used for
the transmitter PCS.
In non-bonded configurations, the receiver 10G PCS uses only the parallel clock
(recovered) for all its blocks.
Parallel clock (recovered) from the CDR in the PMA
Parallel clock from the clock divider used by the transmitter PCS for that channel
lists the different clock sources that are available for each block in the
Parallel clock (recovered)
Write side: parallel clock (recovered)
Read side: parallel clock from the clock divider
If rate matcher is not used: parallel clock (recovered)
If rate matcher is used: parallel clock from the clock divider
Write side:
■
■
Read side: Divided down version of the write side clock depending on the
deserialization factor of 1 or 2, also called the parallel clock (divided)
Parallel clock (divided)
Write Side: Parallel clock (divided). This clock is also forwarded to the FPGA fabric
Read Side: Clock sourced from the FPGA fabric
Regular mode: parallel clock (recovered)
Loopback mode: parallel clock from the clock divider
If rate matcher is not used: parallel clock (recovered)
If rate matcher is used: parallel clock from the clock divider
Transceiver Loopback Support in Stratix V Devices
Clock Source
Chapter 2: Transceiver Clocking in Stratix V Devices
(1)
chapter.
May 2011 Altera Corporation
Internal Clocking