DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 453

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 3: Transceiver Reset Control in Stratix V Devices
Transceiver Reset Sequence
May 2011 Altera Corporation
Reset Sequence for CDR in Manual Lock Mode
In manual lock mode, you are responsible for monitoring all the status signals and
asserting the appropriate reset signals. In case of loss of signal or loss of the reference
clock, you must assert the necessary reset signals.
Figure 3–3
manual lock mode. You must manually perform the reset sequence for the receiver
datapath by asserting rx_set_locktoref high, waiting for the status
rx_is_lockedtoref to go high and then asserting rx_set_locktodata high.
shows the timing diagram of the transceiver reset sequence for CDR in
Stratix V Device Handbook Volume 3: Transceivers
3–5