DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 25

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Stratix V Device Family Overview
Automatic Single Event Upset (SEU) Error Detection and Correction
Automatic Single Event Upset (SEU) Error Detection and Correction
HardCopy V Devices
June 2011 Altera Corporation
Stratix V devices offer new SEU error detection and correction circuitry that is robust
and easy to use. The correction circuitry includes protection for configuration RAM
(CRAM) programming bits and user memories. The CRAM is protected by a
continuously running cyclical redundancy check (CRC) error detection circuit with
integrated ECC that automatically corrects one or two errors and detects higher order
multi-bit errors. When more than two errors occur, correction is available through a
core programming file reload that provides a complete design refresh while the FPGA
continues to operate.
Furthermore, the physical layout of the FPGA is optimized to make the majority of
multi-bit upsets appear as independent single- or double-bit errors, which are
automatically corrected by the integrated CRAM ECC circuitry. In addition to the
CRAM protection in Stratix V devices, the user memories include integrated ECC
circuitry and are layout-optimized to enable error detection of 12-bit errors and
correction for 8-bit errors.
HardCopy V ASICs offer the lowest risk and lowest total cost in ASIC designs with
embedded high-speed transceivers. You can prototype and debug with Stratix V
FPGAs, then use HardCopy V ASICs for volume production. The proven turnkey
process creates a functionally equivalent HardCopy V ASIC with or without
embedded transceivers to meet all timing constraints in as little as 12 weeks.
The powerful combination of Stratix V FPGAs and HardCopy V ASICs can help you
meet your design requirements. Whether you plan for ASIC production and require
the lowest-risk, lowest-cost path from specification to production or require a cost
reduction path for your FPGA-based systems, Altera provides the optimal solution
for power, performance, and device bandwidth.
Stratix V Device Handbook
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