DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 263

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 7: External Memory Interfaces in Stratix V Devices
Stratix V External Memory Interface Features
Figure 7–8. Avoiding Glitch on a Non-Consecutive Read Burst Waveform
May 2011 Altera Corporation
Postamble Enable
dqsenable
DQS
DQS Postamble Circuitry
For external memory interfaces that use a bidirectional read strobe (DDR3 and
DDR2 SDRAM), the DQS signal is low before going to or coming from a
high-impedance state. The state in which DQS is low, just after a high-impedance
state, is called the preamble; the state in which DQS is low, just before it returns to a
high-impedance state, is called the postamble. There are preamble and postamble
specifications for both read and write operations in DDR3 and DDR2 SDRAM. The
DQS postamble circuitry ensures that data is not lost if there is noise on the DQS line
during the end of a read operation that occurs while DQS is in a postamble state.
Stratix V devices have dedicated postamble registers that you can control to ground
the shifted DQS signal used to clock the DQ input registers at the end of a read
operation. This ensures that any glitches on the DQS input signals during the end of a
read operation that occurs while DQS is in a postamble state do not affect the DQ IOE
registers.
In addition to the dedicated postamble register, Stratix V devices also have an HDR
block inside the postamble enable circuitry. Use these registers if the controller is
running at half the frequency of the I/Os.
Using the HDR block as the first stage capture register in the postamble enable
circuitry block is optional. The HDR block is clocked by the half-rate
resynchronization clock, which is the output of the I/O clock divider circuit. There is
an AND gate after the postamble register outputs to avoid postamble glitches from a
previous read burst on a non-consecutive read burst. This scheme allows half-a-clock
cycle latency for dqsenable assertion and zero latency for dqsenable deassertion (refer
to
Figure
7–8).
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Postamble
Postamble glitch
Preamble
Delayed by
1/2T logic
7–19